// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  gicr_vlpi_regs_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/05/11 14:50:32 Create file
// ******************************************************************************

#ifndef __GICR_VLPI_REGS_REG_OFFSET_FIELD_H__
#define __GICR_VLPI_REGS_REG_OFFSET_FIELD_H__

#define GICR_VLPI_REGS_GICR_VSETLPI_PID_LEN    16
#define GICR_VLPI_REGS_GICR_VSETLPI_PID_OFFSET 16
#define GICR_VLPI_REGS_GICR_VSETLPI_VID_LEN    16
#define GICR_VLPI_REGS_GICR_VSETLPI_VID_OFFSET 0

#define GICR_VLPI_REGS_GICR_VSETLPI_VPT_LEN    32
#define GICR_VLPI_REGS_GICR_VSETLPI_VPT_OFFSET 0

#define GICR_VLPI_REGS_GICR_VCLRLPI_VID_LEN    32
#define GICR_VLPI_REGS_GICR_VCLRLPI_VID_OFFSET 0

#define GICR_VLPI_REGS_GICR_VCLRLPI_VPT_LEN    32
#define GICR_VLPI_REGS_GICR_VCLRLPI_VPT_OFFSET 0

#define GICR_VLPI_REGS_GICR_VPROBASER_L_LEN         20
#define GICR_VLPI_REGS_GICR_VPROBASER_L_OFFSET      12
#define GICR_VLPI_REGS_GICR_VPROSHAREABILITY_LEN    2
#define GICR_VLPI_REGS_GICR_VPROSHAREABILITY_OFFSET 10
#define GICR_VLPI_REGS_GICR_VPROCACHEABILITY_LEN    3
#define GICR_VLPI_REGS_GICR_VPROCACHEABILITY_OFFSET 7
#define GICR_VLPI_REGS_GICR_VIDNOB_LEN              5
#define GICR_VLPI_REGS_GICR_VIDNOB_OFFSET           0

#define GICR_VLPI_REGS_GICR_VPROBASER_H_LEN    16
#define GICR_VLPI_REGS_GICR_VPROBASER_H_OFFSET 0

#define GICR_VLPI_REGS_GICR_VPENDBASER_L_LEN         16
#define GICR_VLPI_REGS_GICR_VPENDBASER_L_OFFSET      16
#define GICR_VLPI_REGS_GICR_VPENDSHAREABILITY_LEN    2
#define GICR_VLPI_REGS_GICR_VPENDSHAREABILITY_OFFSET 10
#define GICR_VLPI_REGS_GICR_VPENDCACHEABILITY_LEN    3
#define GICR_VLPI_REGS_GICR_VPENDCACHEABILITY_OFFSET 7

#define GICR_VLPI_REGS_GICR_VPENDBASER_VALID_LEN     1
#define GICR_VLPI_REGS_GICR_VPENDBASER_VALID_OFFSET  31
#define GICR_VLPI_REGS_GICR_VPENDBASER_CGMI_LEN      1
#define GICR_VLPI_REGS_GICR_VPENDBASER_CGMI_OFFSET   30
#define GICR_VLPI_REGS_GICR_VPENDBASER_PDLAST_LEN    1
#define GICR_VLPI_REGS_GICR_VPENDBASER_PDLAST_OFFSET 29
#define GICR_VLPI_REGS_GICR_VPENDBASER_DIRTY_LEN     1
#define GICR_VLPI_REGS_GICR_VPENDBASER_DIRTY_OFFSET  28
#define GICR_VLPI_REGS_GICR_VPENDBASER_H_LEN         16
#define GICR_VLPI_REGS_GICR_VPENDBASER_H_OFFSET      0

#define GICR_VLPI_REGS_GICR_VINVLPI_VID_LEN    32
#define GICR_VLPI_REGS_GICR_VINVLPI_VID_OFFSET 0

#define GICR_VLPI_REGS_GICR_VINVLPI_VPT_LEN    32
#define GICR_VLPI_REGS_GICR_VINVLPI_VPT_OFFSET 0



#define GICR_VLPI_REGS_GICR_VINVALLLPI_VPT_LEN    32
#define GICR_VLPI_REGS_GICR_VINVALLLPI_VPT_OFFSET 0

#define GICR_VLPI_REGS_GICR_VSYNCR_BUSY_LEN    1
#define GICR_VLPI_REGS_GICR_VSYNCR_BUSY_OFFSET 0

#define GICR_VLPI_REGS_GICR_VSRC0_PA_L_LEN    16
#define GICR_VLPI_REGS_GICR_VSRC0_PA_L_OFFSET 16

#define GICR_VLPI_REGS_GICR_VSRC0_PA_H_LEN    16
#define GICR_VLPI_REGS_GICR_VSRC0_PA_H_OFFSET 0

#define GICR_VLPI_REGS_GICR_VSRC1_PA_L_LEN    16
#define GICR_VLPI_REGS_GICR_VSRC1_PA_L_OFFSET 16

#define GICR_VLPI_REGS_GICR_VSRC1_PA_H_LEN    16
#define GICR_VLPI_REGS_GICR_VSRC1_PA_H_OFFSET 0

#define GICR_VLPI_REGS_GICR_VSRC2_PA_L_LEN    16
#define GICR_VLPI_REGS_GICR_VSRC2_PA_L_OFFSET 16

#define GICR_VLPI_REGS_GICR_VSRC2_PA_H_LEN    16
#define GICR_VLPI_REGS_GICR_VSRC2_PA_H_OFFSET 0

#define GICR_VLPI_REGS_GICR_VDEST0_PA_L_LEN    16
#define GICR_VLPI_REGS_GICR_VDEST0_PA_L_OFFSET 16
#define GICR_VLPI_REGS_GICR_VDEST0_PID_LEN     16
#define GICR_VLPI_REGS_GICR_VDEST0_PID_OFFSET  0

#define GICR_VLPI_REGS_GICR_VDEST0_PA_H_LEN    16
#define GICR_VLPI_REGS_GICR_VDEST0_PA_H_OFFSET 0

#define GICR_VLPI_REGS_GICR_VDEST1_PA_L_LEN    16
#define GICR_VLPI_REGS_GICR_VDEST1_PA_L_OFFSET 16
#define GICR_VLPI_REGS_GICR_VDEST1_PID_LEN     16
#define GICR_VLPI_REGS_GICR_VDEST1_PID_OFFSET  0

#define GICR_VLPI_REGS_GICR_VDEST1_PA_H_LEN    16
#define GICR_VLPI_REGS_GICR_VDEST1_PA_H_OFFSET 0

#define GICR_VLPI_REGS_GICR_VDEST2_PA_L_LEN    16
#define GICR_VLPI_REGS_GICR_VDEST2_PA_L_OFFSET 16
#define GICR_VLPI_REGS_GICR_VDEST2_PID_LEN     16
#define GICR_VLPI_REGS_GICR_VDEST2_PID_OFFSET  0

#define GICR_VLPI_REGS_GICR_VDEST2_PA_H_LEN    16
#define GICR_VLPI_REGS_GICR_VDEST2_PA_H_OFFSET 0

#define GICR_VLPI_REGS_GICR_VMOVLPI0_VID_LEN    32
#define GICR_VLPI_REGS_GICR_VMOVLPI0_VID_OFFSET 0

#define GICR_VLPI_REGS_GICR_VMOVLPI0_TA_LEN    32
#define GICR_VLPI_REGS_GICR_VMOVLPI0_TA_OFFSET 0

#define GICR_VLPI_REGS_GICR_VMOVLPI1_VID_LEN    32
#define GICR_VLPI_REGS_GICR_VMOVLPI1_VID_OFFSET 0

#define GICR_VLPI_REGS_GICR_VMOVLPI1_TA_LEN    32
#define GICR_VLPI_REGS_GICR_VMOVLPI1_TA_OFFSET 0

#define GICR_VLPI_REGS_GICR_VMOVLPI2_VID_LEN    32
#define GICR_VLPI_REGS_GICR_VMOVLPI2_VID_OFFSET 0

#define GICR_VLPI_REGS_GICR_VMOVLPI2_TA_LEN    32
#define GICR_VLPI_REGS_GICR_VMOVLPI2_TA_OFFSET 0

#endif // __GICR_VLPI_REGS_REG_OFFSET_FIELD_H__
